| 摘要 |
<p>High density time division busses suffer from many problems, one of which is that impedance discontinuities (LO, CB; Fig. 10) cause signal reflections to occur along the bus. These reflections, in turn, affect the settling time and noise margins of the bus and thus reduce the time "window" in which valid signals may be received. There is disclosed a transmission bus structure (Fig. 12) which allows for bidirectional, multi-port operation by using current drivers (Do/, D1, D3) instead of the traditional voltage drivers for placing data signals on the bus (Lo/, L1, L3). The transmission bus is designed in a manner which allows transmission and reception from a signal clock (501; Fig. 5) on the same clock edge, thereby substantially increasing the time allowed for transmission response and also simplifying the clock distribution requirements (Fig. 12). </p> |
