发明名称 ARITHMETIC SEQUENCE UNIT
摘要 PURPOSE:To prevent a wasteful time consumption when a prefix conversion is unnecessary, and to execute at a high speed a processing of a multi-processor system by executing a directory check simultaneously with a check with respect to whether a prefix conversion is necessary or not, and the prefix conversion. CONSTITUTION:In a multi-processor system which uses a main storage in common and executes a simultaneous parallel operation, a deciding circuit 14 outputs a prefix conversion unnecessary deciding output PREFIX of a high level by a zero detector 18 for detecting all ''0'' of a higher order prescribed bit of a real address converted from a logical address of the first register 10, a comparator 16 for detecting the coincidence of said higher order bit and contents of a prefix register 12, and the like. A directory check by a directory 36 is simultaneously executed, and a bit signal, etc. are outputted through a gate 38 opened by the output PREFIX. Only when the prefix conversion is necessary, a result of the directory check is cut off, an access is executed by a prefix converting output by a register 32, and a wasteful consumption time is prevented.
申请公布号 JPS5998368(A) 申请公布日期 1984.06.06
申请号 JP19820209026 申请日期 1982.11.29
申请人 TOSHIBA KK 发明人 EGUCHI KAZUTOSHI
分类号 G06F12/00;G06F12/08;G06F13/00;G06F15/16;G06F15/177 主分类号 G06F12/00
代理机构 代理人
主权项
地址