发明名称 MEMORY PREFETCH CONTROL SYSTEM
摘要 PURPOSE:To prevent the occurrence of a memory access where a channel exceeds a page, by stopping the prefetch request from a memory requesting circuit when the boundary of the page is detected by a page boundary detecting circuit. CONSTITUTION:If a memory address counter 100 exceeds the boundary of one page in a virtual storage space to designate an address higher than a prescribed address during the execution of data transfer control, the signal of a prescribed bit on the counter 100 is changed from ''0'' to ''1''. As the result, a D type FF constituting a page boundary detector 120 is set by signal ''1'' of the memory address, and the inverted Q output signal is reduced to ''0''. Consequently, a gate circuit 130 is closed after this time to inhibit the output of a memory request signal MREQ. Thus, prefetch of data stored in a main memory is stopped. Meanwhile, the transfer of data stored in a data buffer is terminated when the number of bytes of data transferred to an I/O device reaches a prescribed value
申请公布号 JPS5994128(A) 申请公布日期 1984.05.30
申请号 JP19820202018 申请日期 1982.11.19
申请人 TOSHIBA KK 发明人 KIHARA JIYUNICHI
分类号 G06F13/12;G06F3/00;(IPC1-7):06F3/00 主分类号 G06F13/12
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