| 摘要 |
PURPOSE:To make redundancy less than the case where an individual error detecting code is provided by adding the error detecting code in common to both digital data of one block and address data changing regularly and representing the order of the digital data. CONSTITUTION:The error detecting code, e.g., parity codes P, Q of adjacent codes, are added to an identification signal at each block, address data and data to perform recording. This reproducing signal is supplied to a channel decoder 2, reproducing data converted to 1 word, 8 bits appears at the output, the data is supplied to a TBC (time axis compensating circuit) 3, where the time axis fluctuation of the reproducing signal is eliminated. The output of the TBC3 is supplied to an ID/AD interpolating circuit 4. The ID/AD interpolating circuit 4 reproduces completely a correct identification signal and a correct address data at the normal reproduction, they are supplied to an error correction circuit 5, and after the error correction and detection are performed with respect to the data, the data is supplied to an error detecting circuit 6, and the error detection to the identification signal, address data and data is performed. |
