发明名称 |
SELF-TEST SET |
摘要 |
The LSSD scan paths of each logic circuit chip on a circuit module are connected to additional test circuit chips on the same module. The test chips contain a random signal generator and data compression circuit to perform random stimuli signature generators and also contain switching circuits to connect the scan paths of the chips in parallel between different stages of the random signal generator and the data compression means for random stimuli signature generators and to disconnect the scan paths from the signal generator and data compression circuitry and arrange them serially in a single scan path to perform other tests. |
申请公布号 |
JPS5988664(A) |
申请公布日期 |
1984.05.22 |
申请号 |
JP19830171425 |
申请日期 |
1983.09.19 |
申请人 |
INTERN BUSINESS MACHINES CORP |
发明人 |
UIRIAMU HAWAADO MATSUKANII |
分类号 |
G01R31/28;G01R31/317;G01R31/3185;G06F11/22;H01L21/66;H01L21/822;H01L27/04 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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