| 摘要 |
PURPOSE:To prevent a parasitic MOS transistor without increasing a chip area by covering the tip of the P-N junction surface by the first wiring and the second wiring so that parts of them are overlapped, and applying a high voltage on the wiring layers. CONSTITUTION:A p<+> diffused base 2, an n<+> diffused emitter 3, and a collector lead portion 4 are formed on an n<-> silicon substrate or an n<-> epitaxial layer 1. Then, a surface wiring film 5 comprising SiO2 is formed; and the first Al wiring layers 6-8 are formed; so that they are contacted with the electrode lead portions of the emitter, the base, and the collector; and are extended on an insulating film. Furthermore, the second Al wiring layer 11 are formed on an interlayer insulating layer 9 so that the second Al wiring layer 11 covers the surface of the emitter junction and the base junction, and is overlapped with the first Al wiring layer. On said second wiring layer 11, a high potential is applied to prevent the P<-> inversion 12 due to a parasitic MOS transistor. |
