| 摘要 |
PURPOSE:To perform a division, by providing registers having shift functions for dividend, divisor and quotient respectively to divide repetitively the divisor by the dividend, and supplying 1 or 0 to a bit of the lowest-order of the quotient register in response to the value of the register. CONSTITUTION:The dividend and divisor are set to registers 1 and 2 respectively, and a register 3 of the quotient is cleared. The value of the register 2 is subtracted 4 from the value of the register 1. When the value of the register 1 is larger by a digit than the value of the register 2, the arithmetic result is shifted by a bit to the upper place and then set to the register 1 by a selecting circuit 6. At the same time, logic value is shifted into the lowest bit of the register 3. If the value of the register 1 is smaller than the value of the register 2 by >=1 digit, the data of the register 1 is shifted to the upper place. At the same time, logic value zero is shifted into a bit of the lowest-order of the register 3. In such a way, a high-speed division is possible with a simple circuit. |
