| 摘要 |
PURPOSE:To prevent transmission delay by Mirror effect by separating the wirings for electrical signals which are changed each other in the relation of reversed phase and arranging approximately the lines for sub-signals sent from the same signal source. CONSTITUTION:The ground wire GND, 4-bit signal lines A1-A4, B1-B4, clock phi1, power supply line Vcc are approximately wired in parallel on a SOS substrate, and the signal lines A1-A4 are connected to the poly-Si leadout lines D1-D4 through windows C1-C4. Simultaneously, the signal lines A1-A4 in which signals may be changed reversely are not approximated and the signal lines B1-B4 in which signals may change in the other timings are alternately provided. Thereby, the rising/falling times can be improved by about 40% or more due to reduction of effective capacitance between the adjacent wirings. For the signal lines A0-A2, the sub-signal lines A01-A22 are respectively disposed in both sides of wiring. For A1, the same electrical signal is applied to A11, A12 and a current of A11, A22 is set to 1/2 of A1. At this time, operation of A1 occurs quicker than that of A11, A12 and the rising/falling time is improved by 70% or more than the conventional time. This structure is very effective for IC having a small capacity of wiring to the ground and a large wiring capacitance and is capable of remarkably improving signal delay. |
