| 摘要 |
<p>A variable delay memory system (200) has an addressable memory means (66-1) having a data input port and a data output port. A counter (206) is connected to supply a write address on bus (212) for storage of data supplied to the data input port on bus (64-1). A subtracter means (214) is connected to receive the write address as means (214) is connected to receive the write address as one input on bus (210) and a second input proportional to a desired delay time on bus (72-1). The subtracter means (214) is connected to supply its output as a read address on bus (216) for data stored in the memory means (66-1) to be supplied at the data output port on bus (76-1). The variable delay memory system (200) is particularly adapted for use of its addressable memory means (66-1) as a delay line in an ultrasonic imaging system (50) with the second input proportional to a desired delay time being supplied by a correlator (70) on the basis of cross-correlations between the RF signals supplied on bus (64-1) and the RF signals supplied on corresponding buses (64-2) through (64-21) for other variable delay memory systems connected to the other channels of the ultrasonic imaging system (50). </p> |
