Arithmetic operation circuit

摘要

There is disclosed an arithmetic operation circuit including an adder for performing a multiplication and a division. A one stage arithmetic cell group is formed by connecting eight arithmetic cells. Eight stage arithmetic cell groups are set in the obliquely shifted arrangement and a ninth arithmetic cell group is provided corresponding to the shifts of their arithmetic cell groups in the array. A partial carry circuit is connected to the respective arithmetic cell groups. The arithmetic cells are all comprised of complementary MOS gates and the carry circuit is comprised of enhancement/depletion type MOS gates.