| 摘要 |
Known serial methods solve this by subdividing the information flow into words with the same number of bits, word-by-word checking for equal weighting of the 0-bits with respect to the 1-bits, possible inverting of at least one word for restoring missing equilibrium and marking the inverted word by an additional bit per word which is inserted in each case. To achieve a higher recoding speed, the circuit arrangement provides a weighting circuit B at which the words with the same number of bits, formed by subdividing the information flow phi 1 into n part-flows < phi 1/n>, are present in parallel and in which the number of 1-bits per word are determined in parallel processing and are forwarded as binary number Xi to a first comparison circuit (V1) which determines whether Xi is greater than or less than <n+1/2>. Furthermore, a second comparison circuit (V2), a logic consisting of two AND gates (U1, U2) and one OR gate (O1) for generating an inverting instruction, an adding circuit (A) and a parallel/serial converter (PSW) are provided which recombines the n-fold divided information flow after buffer storage in a second memory (SP2) and - as determined by the inverting instruction (INV) supplied by the logic via a third memory (SP3) ... Original abstract incomplete. <IMAGE>
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