发明名称 PEAK DETECTING CIRCUIT
摘要 PURPOSE:To eliminate the effect of temperature, by subtracting an output and an input of a latch circuit as a subtractor and taking a borrow signal of the subtractor as a reading clock of the latch circuit so as to detect a maximum or a minimum value of an input signal. CONSTITUTION:An input signal of n-bit is stored temporarily in a latch 4, and an output signal of the latch 4 is applied to an adder 6. Further, the input signal is applied to the adder 6 via an inverter 5. The inverter 5 and the adder 6 form the subtractor, and when the input signal is larger than the output signal of the latch 4, the carry output of the adder 6 is brought into 0 and when smaller, brought into 1. When this carry output is at 0, a read clock is applied to the latch 4, the storage of the maximum value of the input signal is made possible and the constitution of a maximum peak detecting circuit is simplified.
申请公布号 JPS5950611(A) 申请公布日期 1984.03.23
申请号 JP19820161736 申请日期 1982.09.16
申请人 MATSUSHITA DENKI SANGYO KK 发明人 SAKASHITA HIROHIKO;YASUMOTO YOSHIO
分类号 H03K5/13;H03K6/00 主分类号 H03K5/13
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