PULL-IN CIRCUIT OF DIGITAL PHASE LOCKED LOOP

摘要

The present invention relates to a digital phase locked loop circuit, particularly to such a circuit which realizes accurately digital phase locked loop pull-in operation at a high speed and with a simplified circuit structure. In the present invention, in order to obtain a phase difference between a single frequency signal and the digital phase locked loop clock signal obtained by dividing the specified frequency signal with dividing counter, such phase difference is obtained in accordance with the signs, absolute values and amplitude ratio of two adjacent sample values taken from the single frequency signal at two points of said digital phase locked loop clock signal corresponding to a phase difference of .pi./2 radians of said single frequency signal. A fast pull-in of the digital phase locked loop is realized by setting a value in the dividing counter corresponding to the obtained phase difference.