| 摘要 |
PURPOSE:To obtain a frequency comparator of a fail-safe type which provides a signal in a fixed direction for a circuit fault, by putting a timing clock for checking between both right and left shift operations and checking the state in a shift register. CONSTITUTION:A gate 22 is inputted with TP0 and TP6 and reads the state of the output to be obtd. at the rise of TP6 into a DT flip-flop 23 during the inversion check of the output. A universal shift register 16 is further latched by the signals TP0 and TP1. The output state is then made invariable but the output result in the latched state is read again into the DT flip-flop 24 at the rise of the signal TP0. As a result of such operation, the output of the flip-flop 23 goes to 1 in the first reading at the rise of the signal TP6 if the OC output is 0 and goes to 0 at the second reading at the rise of the TP0 on account of the left or right shifting. If the OC output is 1, the output of the flip-flop goes to 0 at the first reading and goes to 1 at the second reading. |
