A data processing system consisting of subunits

摘要

When requests are present from several subunits (for example processors) for a unit (for example system bus or memory) each subunit receives access to the unit in accordance with a priority identification (P). For this purpose, a priority circuit (13) is in each case allocated to each subunit, which circuits can be integrated on chips separate from the subunits. The priority circuits (13) are connected to one another via a common bus (14) via which a seizure signal (BB) is transmitted when the unit is seized by a subunit, a request signal (AF) by a subunit and a signal (AFS) proportional to the number of simultaneously requesting subunits are transmitted. The priority circuit examines the priority identification (P) bit by bit and only generates a selection signal (AWS) when the bit of the priority identification is a binary 1 and not more than one subunit provides a request signal. <IMAGE>