发明名称 PROCESS CONTROL DEVICE
摘要 PURPOSE:To reduce an area to be controlled by inserting a parallel connection consisting of a primary delay element and a primary advance element between a PID controller and a process. CONSTITUTION:A parallel circuit B consisting of a primary advance element 19 and a primary delay element 20 is inserted between the proportional integration/ differentiation PID controller A including a proportional element 14, a differentiation element 15 and an integration element 16 and a process C including an equivalent idle time element 11, an adder 12 and the primary delay element. The elements 19, 20 are expressed by formulas 1 and 2 respectively and these outputs are added by an adder 21 and outputted as a manipulated variable. If it is defined that the equivalent idle time element of the element 11 is 1/(1+L2) and (n) is an optional integer, the controlled area shown by the controlled variable and time can be reduced less than a prescribed value by selecting (n).
申请公布号 JPS5941006(A) 申请公布日期 1984.03.07
申请号 JP19820152380 申请日期 1982.08.31
申请人 SHIMAZU SEISAKUSHO KK 发明人 UCHIDA YOSHIHISA
分类号 G05B11/36;(IPC1-7):05B11/36 主分类号 G05B11/36
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