| 摘要 |
PURPOSE:To shorten remarkably the number of machine cycles, by suppressing an output of a two-input adder placed in parallel with a three-input adder to zero, so that it can be inputted instead of the first input among three inputs. CONSTITUTION:Input information A held by an input register 51 is selected by a switch 41, and is provided to a two-input adder 72. Input information B held by an input register 52 is provided to the two-input adder 72. Its output is held by an address register 62. In the following cycle, the output of the address register 62 passes through a data bus 30, is provided to the switch 41, zero suppression information by which lower three bits are set to zero forcibly is formed, and the input register 52 is reset. The contents of the input registers 51-53 are passed through the data buses 25-27 as operating information, are inputted to a three-input adder 71 and are added, and its output is held by an address register 61 through a data bus 31. |
