| 摘要 |
PURPOSE:To form a testing logic pattern preventing increase in delay in the propagation a gate group by a specified logic processing while decoding an external input signal. CONSTITUTION:Signals x1-x4 and complementary signals thereto are outputted from a decoder 4 with decode circuits 41-44 according to four inputs or the like x1-x4 and control input signal v1-v2. Based on these signals, computation of Reed-Mahler's expansion is performed with a gate group to which a logic constant y1 is applied with an AND circuit 1 and an exclusive OR gates 231-234 to form a universal test pattern signal according to the combination of the signals x1, x2, x3 and x4, thereby facilitating the inspection of signal logic degeneration trouble and single short-circuit trouble of a signal line performing a wired AND or OR function. The structure using a decode output halves the number of exclusive OR gates as compared with the exclusive OR processing of an AND output of the inputs x1-x4 and the inputs x1-x4, thereby affording an easy- to-inspect logic circuit with a limited delay in the propagation of a gate group. |
