发明名称 RETRIAL CONTROL SYSTEM
摘要 PURPOSE:To guarantee the propriety of retrial in any case, by executing sequentially retrial in the preset retrial unit, based on the function check mode set with a retrial mode setting circuit. CONSTITUTION:A retrial control circuit 14, a retrial mode control circuit 15 and a save circuit 17 and the like are provided. When a retrial timing circuit 19 in the circuit 15 indicates the timing of the 1st to the final step of each machine instruction, a retrial processing routine start signal 111 is generated at each machine instruction and the processing is performed while the retrial of each machine instruction is repeated. When a check point is selected to a point of time during the flow of processing, the processing is interrupted forcedly before the check point of the next point of time is selected, the saved data is restored and the processing is retried from the check point. When the check point of the next point of time is selected, the processing is repeated similarly and the retrial unit is retried once without fail.
申请公布号 JPS5920054(A) 申请公布日期 1984.02.01
申请号 JP19820129882 申请日期 1982.07.26
申请人 FUJITSU KK 发明人 IWATA KATSUYUKI
分类号 G06F11/14 主分类号 G06F11/14
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