Semiconductor memory device with redundancy decoder circuit.

摘要

A semiconductor memory device includes a redundancy decoder circuit (11). The redundancy decoder circuit (11) includes depletion type FAMOS transistors (41-44) to which an address pattern, corresponding to an address of a defective memory cell to be replaced by a redundancy memory cell, is written at their floating gates (FG). Control gates of the FAMOS transistors (41-44) receive a voltage having a ground level or lower during a normal memory access mode.