| 摘要 |
A phase locked loop system for receiving a data input with a predetermined bit frequency includes a source (10 D1 D2) of clock signals with a frequency nominally equal to the bit frequency of the data signal means (12,13,14,15,16) for dividing each clock period into three regions corresponding to early, normal and late arrival of the data signal relative to the clock signal and means (D3 D4 D5) for deciding which region the data signal occurs in and for respectively advancing or retarding the phase of the clock signal if the data signal occurs in the early or later region. |
