| 摘要 |
<p>PURPOSE:To deliver both clock and pulse signals after switching them by the desired timing by selecting the clock signal through a selector and stopping this signal after an optional number of clocks. CONSTITUTION:The clock signal received from a clock oscillator 1 is usually selected and '0' is always loaded to a counter 7 with the signal received from a start switch 8 and kept at 'L'. Then the level of comparator 9 and the output of an AND gate 11 are set at 'L'. The clock signal received from a selector emerges at the output 6 of an OR gate 5. The signal of the enable terminal of a counter is set at 'H' when the signal of the switch 8 is set at 'H'. Thus the clocks are counted and the comparator 9 is set at 'H' when the count value of clocks exceeds a set level 10. Then the OR output is set at 'H' as long as the signal of a control switch 13 is kept at 'H' with the enable terminal set at 'L' respectively. Thus the clock count value and the OR output are held. While the pulse signal received from a manual switch 2 is selected 3 and the signal 13 is set at 'L'. Then the pulse signal is delivered from a gate 5.</p> |
