| 摘要 |
PURPOSE:To obtain the multi-gate Schottky barrier FET enabled to perform high speed logic operation by a method wherein gate electrodes of two pieces or more are provided between electrodes of a source and a drain, and the more the gate electrode approaches the drain electrode from the source electrode, the more the gate width is broadened. CONSTITUTION:Si ions are implanted to a semiinsulating GaAS substrate to provide an N type active layer 10, and width thereof is made to have the trapezoid type extending toward the drain electrode 14 from the source electrode 13. The AuGeNi source electrode 13 is formed at the upside thereof, the drain electrode 14 of the same is formed at the downside, the parallel two lines type Al Schottky electrodes 11, 12 are formed between them, and the electrode 12 is made longer than the electrode 11. Otherwise, an island type ohmic electrode 15 is inserted between the gates 11, 12, and to make the series type FET's having different gate width is also favorable. By changing gate width like this, the difference between source series resistances according to the gate electrodes is compensated, the difference between transmission delay times according to the positions of the gate electrodes is reduced, apparent gm of each electrode is made the same, and the multigate FET having high maximum operating frequency and moreover having stable operation can be obtained. |
