Dataprocessing system with virtual subaddressing of the buffer memory

摘要

The virtual subaddressing of the data buffer subdivided into several banks or pages of equal size and of the tag/flag memories in each case associated with one of these data buffers and used for storing the page addresses is done in such a manner that the real class address is extended by n virtual additional bits of the page address for addressing data buffer banks having in each case 2<n>-times the page capacity. Furthermore, several duplicate tag/flag memories (TFD1), associated with the respective original tag/flag memories (TFO1), which are subjected to real addressing also with respect to the n additional bits, and comparison circuits (CO1, DC1) associated with the outputs of the original and duplicate tag/flag memories, are provided in which the real page addresses, or the page address reduced by the n additional bits, are compared with the page address existing in the respective tag/flag memories. Each of the duplicate tag/flag memories associated in each case with one data buffer bank (DB1) consists of 2<n> memory units, each memory unit (TFD1-00, TFD1-01, TFD1-10, TFD1-11) in each case being associated with one of 2<n> bit combinations of the n additional bits. <IMAGE>