| 摘要 |
PURPOSE:To control an HDLC line in a high speed by a CPU in a slow processing speed, by providing two sets of high level data link control (HDLC) reception sections, and switching data and flag pattern inputs alternately. CONSTITUTION:The HDLC reception section is provided with the 1st and the 2nd HDLC reception sections 2, 2A, to each of which a switch circuit 7 is connected. A flag pattern generating circuit 5 is connected to the circuit 7 and an external data line 1 and a detection circuit 6 detecting the frame from the line 1 are connected. A memory 3 storing the data inputted to the sections 2, 2A, and a CPU4 managing the procedure of the HDLC and preparing the reception of the sections 2, 2A are connected to the reception sections 2, 2A. The input data from the line 1 and the flag pattern from the circuit 5 are switched at the circuit 7 alternately and stored in the memory 3, the CPU4 in a slow processing speed is used to process the data of the line 1 in a large speed. |
