PLL TYPE TIMING EXTRACTING CIRCUIT

摘要

PURPOSE:To extract a phase-adjusted clock signal automatically by supplying a variable frequency oscillator with the integrated result of a signal corresponding to the difference between the leading element and lagging element of the phase difference between a digital data signal and a feedback signal. CONSTITUTION:A phase comparator PD200 makes a phase comparison between the digital signal 11 and the feedback signal 22 outputted from a voltage-controlled oscillator VCO207 to output the 1st and the 2nd difference signals 20 and 21 according to the comparison result. The charge pump circuit 202 of an integrating circuit 201 integrates the signals 20 and 21 respectively to find the difference between their integral results and supplies it to the VCO207 through an active filter 203. The VCO207 generates a signal of frequency corresponding to the output voltage of the circuit 201. Then when the signal 22 is varied by the VCO207, the elements of the signals 20 and 21 become equal to each other, and consequently the system is locked.