| 摘要 |
PURPOSE:To eliminate the need for the control of a master CPU and to shorten an interruptive analysis time by the interruption between slave CPUs, by sending the destination address of an interuption request to a system address bus and said address to a data bus. CONSTITUTION:A CPUm-11a accesses a memory 6a normally by a decoder circuit 7a, but when an interuption to the CPU of another data processing part is caused, the address of an interupted CPUm1b is sent to an internal address bus baa and its own address is outputted to the internal data bus bda. When the CPUm-11a obtains the right of using system buses Ba and Bd, the address information (address of CPUm1b) of the CPUm-11a is outputted to the system address bus Ba and the data information (address of CPUm-11a) of the CPUm-11a is outputted to the system data bus Bd. |
