发明名称 PROCESSING SYSTEM OF POWER FAILURE RESTORATION
摘要 PURPOSE:To simplify the circuit, by providing a non-volatile memory for an input/output controller, processing the power restoration of a specific bit patatern for the non-volatile memory at a power failure and using volatile memories for main memory. CONSTITUTION:When an input power supply to a power supply board 4 is failed, a power failure predicting signal 5 is transmitted from the board 4, a processor 1 interrupts the processing during execution at present and performs power failure processing. During the power failure processing, the processor 1 gives a command to the input/output controller 7 and sets a flag, e.g., a flag (50)16 in an RAM 7C. Further, the processor 1 comes to a halt. During the power failure, a power is given to the RAM 7C from a battery 3 and the flag (50)16 remains as set. When the power is restored, the power is applied to the entire device from the board 4, the presence/absence of setting of the flag of the RAM 7C is checked and after the power restoration processing, the processing is transited to the normal processing.
申请公布号 JPS58168121(A) 申请公布日期 1983.10.04
申请号 JP19820051723 申请日期 1982.03.29
申请人 FUJITSU KK 发明人 MOROSAWA KENJI;YOSHIDA SHIYUUJI;HATA MASAHIRO;OKAMURA HARUHIKO;HASHIMOTO ICHIKO
分类号 H02J1/00;G06F1/30 主分类号 H02J1/00
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