Priority resolver circuit.

摘要

A priority resolution circuit has four flip-flops CPF, SIF, CIF, and FIF for the four possible requesting units. Setting a low priority flip-flop, e.g. CPF, prevents later setting of a higher priority one by gates 33 to 35, but a high priority one can be set substantially simultaneously with a low priority one. Output gates CPG, SIG, CIG, select the highest priority flip-flop which is set. The setting of any flip-flop fires a timing circuit by pulse TCF, and this enables the gates CPG, SIG, CIG by pulse CLR after all possible transients have decayed. The timing circuit may have its timing controlled by the selected unit (CPU, SIP, CIP, or MBA) via a selector controlled by the flip-flops CPF, SIF, CIF, and FIF.