发明名称 DIAGNOSING METHOD OF LOGICAL DEVICE
摘要 PURPOSE:To diagnose a logical device independently of in-phase transfer logic, by providing an intermediate latch between an input side latch and an output side latch of a partial circuit to be diagnosed and supplying a proper timing signal to the intermediate latch. CONSTITUTION:A signal 12 influenced by the internal state of a combination circuit 10 is fetched into an output latci 2 by a timing signal 22. Although the prestage unconfirmed value is inputted also to an input latch simultaneously, the unconfirm value is not fetched into the intermediate latch 3 during the rise of the timing signal 22 because a timing signal complementary to the timing signal 22 is supplied to the intermediate latch 3. Simultaneously with the decay of the timing signal 22, the timing signal 23 rises and the unconfirmed value of the input side latch 1 is fetched into the intermediate latch 3. Since the timing signal 22 to the output side latch 2 falls at the same time, the contents of the output side latch 2 is kept at a conformed value.
申请公布号 JPS58139256(A) 申请公布日期 1983.08.18
申请号 JP19820021117 申请日期 1982.02.15
申请人 HITACHI SEISAKUSHO KK 发明人 TAKAHASHI EIJI;HASHIMOTO MASAHIRO;KAWABE TAKASHI;GOTOU FUMIO;KAWASHIMA SEIICHI
分类号 G06F11/22;G06F11/273 主分类号 G06F11/22
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