发明名称 POWER-ON CLEAR CIRCUIT
摘要 <p>PURPOSE:To prevent electrostatic noise and to ensure the operation, by connecting a capacitor and a resistor between one end of a power supply and an output terminal of a boosting circuit in series and connecting a connecting terminal of the capacitor and resistor to an input of an inverter. CONSTITUTION:When a switch 9 is turned on and the circuit is at a steady- state, an inverting potential difference Vss2-Vss between a connecting terminal A and an inverter 3 is large, then a power-on clear circuit is hardly operative. Since a boosting capacitor 8 is connected in parallel with a series circuit between a capacitor 1 and a resistor 2, electrostatic noise is absorbed in the capacitor 8 and the power-on clear circuit is hardly operative due to electrostatic noise. At the application of power supply, after an oscillation circuit 11 and a frequency division circuit 10 are operated, the time required for a boosting terminal B to reach a potential level Vss2 is sufficiently slower than the time required for the inverter 3 to become in a normal operating state, the power-on clear circuit is surely operated.</p>
申请公布号 JPS58137022(A) 申请公布日期 1983.08.15
申请号 JP19820019448 申请日期 1982.02.09
申请人 DAINI SEIKOSHA KK 发明人 SUGIURA KAZUNARI;MATSUURA YOSHIAKI
分类号 H03K17/22;G06F1/24;G06F1/26;(IPC1-7):06F1/00 主分类号 H03K17/22
代理机构 代理人
主权项
地址