发明名称 LOGIC ANALYZER
摘要 PURPOSE:To realize an effective application of the fetched logic signal, by having a display based on the number of clocks counted from the time point of generation of a trigger signal through the discontinuation of working of a storing means. CONSTITUTION:A word recognizer 16, etc. produces a trigger signal in response to the logic signal supplied from a comparator 12. Thus a counter 26 is set in an enable state to start counting the clocks. The counter 26 continues counting for a period during which the storage to a storing means which is performed in response to a manual operation of a keyboard 48 is over and then an AND gate 28 is closed by the inversion of an FF 32. The relation is displayed at a CRT 54 between the input logic signal and the trigger signal which are fetched based on the count value of the counter 26 and the processes carried out via a CPU 20, an ROM 42, an RAM 44, etc. The fetched logic signal is used effectively.
申请公布号 JPS58135462(A) 申请公布日期 1983.08.12
申请号 JP19820016544 申请日期 1982.02.04
申请人 SONII TEKUTORONIKUSU KK 发明人 YOKOGAWA HIDEMI;TAKITA KENTAROU;MANOME TERUO;TSUKAMOTO TAKUROU
分类号 G01R13/28;G06F11/25 主分类号 G01R13/28
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