发明名称 PLL CIRCUIT
摘要 PURPOSE:To realize a stable PLL operation to a signal of a random cycle, by using a voltage control oscillator which receives a phase control with an exclusive OR between the latch output of an input signal and the input signal and at the same time has a latch operation with an oscillation output. CONSTITUTION:An input signal (a) having a random cycle and supplied through an input terminal 1 is applied to a data input D of a latch circuit 2 as well as to a double input exclusive OR circuit EX-OR3. An output (b) of a voltage control oscillator VOC performs a latching operation. The difference of phase between the signal (a) and the output signal (c) of the circuit 2 is applied to a VCO5 via an LPF4 to control the oscillating frequency of the VCO5. In a steady state the VCO5 is locked when a cycle of the output (b) is equivalent to a clock period T. Therefore the pulse width of the output (b) is set at 1/2T in the steady state. Then the signal (a) has a delay phase compared with the output (b). Thus the pulse width of a phase difference (d) is reduced, and a control is given to delay the phase of the output (b).
申请公布号 JPS58130630(A) 申请公布日期 1983.08.04
申请号 JP19820013110 申请日期 1982.01.29
申请人 SANSUI DENKI KK 发明人 TAKAHASHI SUSUMU;KAMEDA HIROMI
分类号 H03L7/08;(IPC1-7):03L7/08 主分类号 H03L7/08
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