发明名称 SEQUENTIAL CONTROL CIRCUIT
摘要 PURPOSE:To prevent a filter effect from being spoiled without generating any individual frequency components by providing circuits for by-passing flip-flops corresponding to an objective system of sequential control supplied with a stop command. CONSTITUTION:At time Tx, when a pulse has a logical level 0, a bypass for an FF8 is formed and pulses B' and C' coincide with each other. Therefore, pulses C' and D' have logical levels 1 and 0 alternately and repeatedly. At this time, pulses H', I', and J' are outputs of AND between pulses B', C', and D', and E, F, and G, so when the E has the logical level 0, the H' has the logical level 0 without fail. Therefore, the signals H', I', and J' which are 120 deg. out of phase with one another when the E has the logical level 1 become signals I' and J' which are 180 deg. out of phase after the time Tx. Namely, when an optional number of output signals are intercepted, the remaining signals are generated automatically with an equal phase difference, preventing a component of individual frequency from appearing at a load side.
申请公布号 JPS58123107(A) 申请公布日期 1983.07.22
申请号 JP19820004970 申请日期 1982.01.18
申请人 TOYO DENKI SEIZO KK 发明人 IWAKUNI SHIYUUZOU;SANO TAKASHI
分类号 G05B19/02;G05B19/07 主分类号 G05B19/02
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