| 摘要 |
PURPOSE:To attain a multiplied frequency with high accuracy and speed, by normalizing signals at a counter function section with a basic clock frequency frequency-divided externally, setting the result in a down-counter and down- counting it with the basic clock. CONSTITUTION:A signal (e) having an input frequency fIN is inputted to a zero cross detection circuit 3 from an input wave source 1 via a waveform shaping filter 2. The zero cross signal is inputted to a delay function part 51 and a latch function part 53 of a signal processing circuit 5 as an interruption signal. An output basic clock C of a basic clock oscillator 6 is frequency-divided into 60kHz at a frequency dividing circuit 7, inputted to a counter function section 52 for count. The basic clock C is inputted to a down counter 8, the result of operation of an operation functing section 54 is loaded to the down counter 8 to obtain a down-counted clock. Every time the counter 8 is reset zero, a signal of the frequency f0 is outputted. |
