| 摘要 |
PURPOSE:To allow a logical circuit by a Josephson element to operate stably and to decrease the number of NOR circuits included in a combinational by NOR operation, by performing sampling operation during the starting of a power source and constituting a latch circuit which outputs an input signal as it is and its inveted signal simultaneously. CONSTITUTION:When an input is O, the power source is turned on at time t1 and once a timing signal is applied to an element A2 at time t2 through the delay of a delay circuit C, the element A2 is placed in a resistive state to send an NOT output through an output resistance RA2 at time t3. When the input is 1, the power source is turned on at time t6 and at this time, the input is already applied to elements A1 and B2, so that both turn into the resistive state to send out the input as it is at time t7 through an output resistance RB2. Although the timing signal is inputted at time t8 through the delay circuit C, the element A1 is already placed in the resistive state, so the element A2 never turns into the resistive state. Even if the input goes down to O at time t9, the elements A1 and B2 are in a latch mode, so neither of them changes in state. |
