发明名称 MULTIPLEX CALCULATOR AND STRUCTURE OF COMMUNICATION BUS USED THEREFOR
摘要 <p>A local system bus, including the necessary address, data and control lines, communicates a local central processor, memory, input/output and control resources forming a first computing system for executing processing operations. A controllable user bus interface circuit selectively couples the local system bus to a user system bus for selected communication therebetween. The user system bus includes the necessary address, data and control lines capable of communicating the user central processor, memory, input output and control resources, organized as a second computing system, for executing processing functions. The user bus interface circuit is controllable to permit undedicated local memory resources to be accessed by the user system bus for data transfer therebetween, undedicated user memory or input/output resource access by the local system bus for data transfers therebetween and isolation of the two system buses from each other. The controllable user bus interface circuit maintains asynchronous separation between the two system buses, which allows separate processing operations to be executed simultaneously on the two system buses whenever there are no transfers across the user bus interface circuit in progress.</p>
申请公布号 JPS58105371(A) 申请公布日期 1983.06.23
申请号 JP19820180073 申请日期 1982.10.15
申请人 KONBAAJIENTO TEKUNOROJIIZU INC 发明人 RICHIYAADO DABURIYU ROUENSARU
分类号 G06F3/00;G06F13/40;G06F15/16;G06F15/173 主分类号 G06F3/00
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