| 摘要 |
A full duplex, synchronous data set (10) includes primary signal processing circuitry which generates a modulated transmit data signal in response to serial data from a terminal interface (17). The modulated data signal is transmitted over a primary channel of a transmit line (11). The primary signal processing circuitry also receives modulated data signals from a primary channel of a receive line (12) and recovers therefrom a serial bit stream for presentation to the interface. The operating parameters of the primary signal processing circuitry are specified by a primary controller (30) over a plurality of buses (PA, PC, PD). The primary controller includes a microprocessor (310) and associated peripherals (315, 320, 325, 330, 335). Encoder (115) and decoder (175) circuits within the primary signal processing circuitry are each comprised of a plurality of modules (1310, 1340, 1440, 1460, 1510, 1710, 1835, 1840, 1960, 1980) each designed to perform a specific function. The modules are operated in a selected sequence, with signals passing from one module to the next via a local bus (LEB, LDB).
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