| 摘要 |
A memory protection arrangement particularly suitable for use with battery backed-up CMOS RAMs. The voltage level of power to the CMOS RAMs is referenced to the logic supply to eliminate latch-up and low voltage problems and to relax the tolerances required in power supply circuits. In addition, the master chip enable for all CMOS RAMs is latched rather than providing a separate latch for individual chip enable. Furthermore, the state of the logic supply is latched at the beginning of each memory cycle to prevent disabling of the CMOS RAMs during a cycle. An additional voltage sensor controls the enable of a buffer for each chip enable.
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