| 摘要 |
PURPOSE:To eliminate erroneous pulses, by gating the detection signal of a frame synchronizing signal by gate pulses having a window width of a pulse width where the length of time of generation of cycle slip is taken into consideration. CONSTITUTION:A high frequency detecting circuit 13 detects whether a reproducing signal exists or not, and this detection output and a mode signal indicated by a system controlling circuit 14 are supplied to a controller 16. The signal from an error correcting circuit 15 is supplied to the controller 16 also. This control signal is supplied detectors 9 and 11 for the counted value of a counter 7, and a counted value corresponding to m-number of bits is changed in accordance with the condition of data error to change the width of window pulse PW. The preset value of a monitor counter 12 is changed by the signal of the controller 16 in accordance with the reproducing mode and the existence detection output of the reproducing signal. |
