| 摘要 |
In this electronic modulo-10 up/down counter (Figure 6), the resetting of the flip flops is also preselected by the internal counting output as in the electronic counter according to the main patent application P 3047169.3. In this electronic counter, the flip flops are combined with negating delay circuits, with the exception of the switching flip flop (6) which is combined with a special monostable flip flop. The flip flop input circuits also consist of two OR gates having two inputs each and four AND gates having two inputs each in this up/down counter. <IMAGE>
|
