发明名称 PHASE LOCKED LOOP AND MIRROR CODE DECODER USING SAME
摘要 A phase-lock loop is disclosed for synchronizing an oscillator signal with a train of input signal pulses, some of which may be missing. The phase-lock loop is of particular use in a decoder for decoding digitally encoded data employing a self-clocking coding scheme. The decoder generates a clock from the input signal stream for use in the decoding process.
申请公布号 JPS5890829(A) 申请公布日期 1983.05.30
申请号 JP19820199148 申请日期 1982.11.15
申请人 ESU AARU AI INTERN 发明人 JIYON MIRUTON YAABOROO JIYUNIA
分类号 H03M5/04;G11B20/14;H03L7/14;H03L7/181;H03L7/199;H04L7/033;H04L25/49 主分类号 H03M5/04
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