| 摘要 |
PURPOSE:To attain the transfer of data while checking the normal property of the data without deteriorating each processing capacity, by eliminating the waiting time for writing/reading to a memory regarding the transfer of data between data processors. CONSTITUTION:For the transfer of data between data processors 1 and 1', a buffer memory 7 is divided into four cycles P1-P4. A buffer memory for transfer of data from the No.0 processor 1 to the No.1 processor 1' is shared with a buffer memory for transfer of data from the processor 1' to the processor 1. Then the I/O instructions given from the processors 1 and 1' are allowed to correspond to each cycle. In such a way, the memory writing registers 3 and 3', the memory reading registers 4 and 4', a parity checking circuit and a parity adding circuit 6 are provided to the processors 1 and 1', respectively. Thus a memory 7 is used in time division to eliminate the waiting for writing/reading to the memory. As a result, the normal property of the data can be checked. |
