| 摘要 |
PURPOSE:To use parallel input data from an external connection device without reference to its bit length by converting the parallel input data in serial data temporarily and then performing bit length conversion. CONSTITUTION:The shift register 2 of a data input device 1 latches input data 11 transferred in parallel from an external connection device by the shift clock signal 15 of a main control part 4, and converts it into serial data, which is transferred to a buffer register 5. Once receiving a control signal 18 from the main control part 4, a selecting circuit 6 fetches bits that the main control part 4 specifies from the buffer register 5 to match the bit length of the input data with that of the input and output bus 8 of a CPU9, and then outputs the data 20 to an input and output bus interface circuit 7. Then, the circuit outputs a control signal 19 to the main control part 4 after said fetching, and holds successive data conversion in readiness. |
