| 摘要 |
PURPOSE:To accelerate the I<2>L element speed without reducing the withstand voltage of linear transistor by a method wherein the epitaxial layer only of I<2>L unit is made thinner. CONSTITUTION:N<+> type embedded layers 2A-2C are provided on P type Si substrate 1A to form N type epitaxial layer 4A. After forming the etching grooves 12A-12C in the separated region utilizing SiO2 film as a mask, Si etching is performed utilizing SiO2 films 100, 101 as a mask making the epitaxial layer of I<2>L unit thinner. Firstly, P type layer 5A is formed by means of ion implantation etc. as a separated region. Secondly, the linear element (NPN transistor) is formd on thick epitaxial layer 4B forming I<2>L element on the thin epitaxial layer 4C. The groove 12 is flattened using PII resin 11, etc. as necessary forming electrodes 9A-9F. Through these procedures, the operational margin of I<2>L element may be secured and accelerated in speed. |
