| 摘要 |
PURPOSE:To scan out the output in a high-speed cycle without increasing the number of input/output pins when the degree of integration of an LSI is enhanced, by providing a binary counter, which is selectively switched to either of the serial input mode or the count mode, in a logic block. CONSTITUTION:Logical gates 52-54 and FFs 55-58 are provided in the inside of a logic block 51 of a scan-out system. Scan addresses are assigned to gates 52-54 and FFs55-58, respectively. In case that optional one of addresses of gates 52-54 and FFs55-58 is scanned out, a mode signal SR/CT of a counter 60 for scan-out is set to a serial input mode SR, and scan addresses given to gates 52-54 and FFs55-58 are applied to the serial input terminal bit by bit and are set into the counter 60 by a scan clock SC applied to the counter 60. The address is selected in a multiplexer 61 by the output of the counter 60, and a scanned-out output result SO is outputted. |
