发明名称 PACKET BUFFER CONGESTION MONITOR SYSTEM
摘要 PURPOSE:To enable a CPU to detect the congestion of packet buffer early, by providing a buffer congestion monitor section for a CCE (communication controller) for the self-monitor and information. CONSTITUTION:A CPU 1 informs a number of use of buffer to a buffer congestion monitor section 5 via a block transfer control section 4 and stores the value to a memory in the section 5. When the section 5 detects that the number of buffer usage reaches a prescribed value or over, the section 5 requests the information of the buffer congestion to the CPU 1 for the section 4. When the CPU 1 receives interruption from a CCE2 and the information of buffer congestion, the CPU 1 gives instruction of the information of the number of buffer usage. The section 4 follows the instruction, receives the report of the number of buffer usage from the buffer congestion monitor section 5 and informs the CPU 1 of it. The CPU 1 checks whether or not the number of usage exceeds a prescribed number every time the information is received and if the CPU 1 exceeds continuously for a prescribed number of times, the input restriction packet is transmitted.
申请公布号 JPS5877351(A) 申请公布日期 1983.05.10
申请号 JP19810176726 申请日期 1981.11.04
申请人 NIPPON DENSHIN DENWA KOSHA 发明人 YOMO YOSHIAKI;YOSHIE KINZABUROU;TAKAGI IWAO
分类号 H04L13/08;G06F12/08 主分类号 H04L13/08
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