Logic having inhibit mean preventing erroneous operation circuit

摘要

A logic circuit operable without erroneous operation is disclosed. The logic circuit comprises a first and a second switching transistor operating in response to the same signal, a first logic gate including an input transistor receiving a signal derived from the first switching transistor and a second logic gate receiving a signal derived from the second switching signal, in which the signal derived from the first switching transistor is independently fed to the first logic gate.