发明名称 SQUELCH CIRCUIT OF SYNCHRONIZING TRANSMITTER AND RECEIVER
摘要 PURPOSE:To keep the input side level less than the normal level for a receiver under transmission and during squelch time, by putting a level controller into the input terminal of the receiver and controlling the level controller with a squelch controlling circuit. CONSTITUTION:A level controller 16 is controlled by a squelch operation controlling signal 14 and through a squelch controlling circuit 13 even while the transmission request signal RS of a terminal is turned on. Thus the signal level is lowered less than the working level of demodulation for the input of a demodulator 7. Therefore the receiving carrier detecting output CD of a terminal 11 is turned off, and the received data RD of a terminal 10 is clamped by a clamping circuit 9. When the signal RS is turned off, the circuit 13 performs a squelch operation. The suppression of the input signal to the demodulator 7 and the control of the controller 16 are eliminated after the squelch time. Thus the circuit 9 is set free. As a result, the CD of the terminal 11 is not turned on, and undesired data is not tramsitted to a device connected to the terminal 10.
申请公布号 JPS5871746(A) 申请公布日期 1983.04.28
申请号 JP19810170321 申请日期 1981.10.23
申请人 NIPPON DENSHIN DENWA KOSHA 发明人 JINBO YOSHIHIRO;NAKAMURA OSAMU;SONEHARA NOBORU
分类号 H04B1/10;H04L5/16 主分类号 H04B1/10
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