| 摘要 |
PURPOSE:To speed up the condition code setting-up timing of a comparison instruction not requiring address calculation by reading out a register specified by the instruction concurrently with the decoding of the instruction and comparing the capacity of the contents. CONSTITUTION:In the 1st cycle, a comparison instruction is set up in a register 1. In the 2nd cycle, an output D1 of a decoder 2 is turned to ''0'' and the contents of a general purpose register in a register memory 3 which correspond to specified codes R1, R2 in the register 1 are read out and stored in registers 6, 7 respectively. Simultaneously a comparator 5 sets up a forecased condition code in a register 11 and a FF 12 is set to ''1''. In the 3rd cycle, a branching propriety decision circuit 14 decides the propriety of branching from a value loaded from the register 11 to the output terminal of a selector circuit 13 and the branching condition mask of a branch instruction stored in the register 1. Consequently a condition code for a comparison instruction which does not require the address calculation of an operand is obtained more quickly, speeding up instruction executing sequence. |
